1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a semiconductor device including selectively forming a gate sidewall spacer.
2. Discussion of the Related Art
In a conventional semiconductor memory device such as a DRAM (Dynamic Random Access Memory), gate sidewall spacers are simultaneously formed in a cell region and a periphery circuit region, using the same process even though these regions require the gate sidewall spacers having characteristics different from each other. As memory devices become more highly integrated, the space between gates in the cell region becomes narrower, requiring a decrease in a length of the gate sidewall spacer. The reduction of the gate length does not affect the cell region, but makes the fabrication of an LDD-structure (Lightly Doped Drain) transistor difficult on the periphery circuit region.
A conventional method of fabricating a semiconductor device will be explained below with reference to the accompanying drawings. FIGS. 1A and 1B are cross-sectional views showing the conventional method of fabricating a semiconductor device. In the conventional fabrication process, the gate sidewall spacer is formed in order to protect the gate and to form an impurity diffusion region of the LDD structure under the gate.
Referring to FIG. 1A, a gate oxide layer 2 is formed on a semiconductor substrate 1, and a gate material layer 3 is formed thereon, using, for example, polysilicon. A cap insulating layer 4 is formed on the gate material layer 3. The cap insulating layer 4, the gate material layer 3, and the gate oxide layer 2 are selectively etched to form a gate electrode.
Referring to FIG. 1B, a material layer for a sidewall spacer is formed on the overall surface of semiconductor substrate 1 (including a cell region and a periphery circuit region) on which the gate electrode is formed, and then etched back, forming sidewall spacers on both sides of the gate electrode. Thereafter, impurity ion implantation is carried out to form a source/drain region using the gate electrode as a mask (not shown).
According to the conventional fabrication process, since the sidewall spacer is simultaneously formed on the cell region and the periphery circuit region, it cannot satisfy the different requirements of the two regions. For a memory device like a DRAM, the sidewall spacer is formed in the periphery circuit region and the cell region under the same process conditions. The sidewall spacer in the cell region is fabricated not to form the LDD structure, but to obtain some margin in such process steps as bit line contact formation and node contact formation.
Furthermore, the process steps performed on the cell region become much more important as the device becomes more highly integrated. Thus, process parameters for the sidewall spacer formation are determined with regard to the overall process margin in the cell region. Accordingly, the periphery circuit region cannot have the sidewall spacer with optimal characteristics.
The cell region and the periphery circuit region require sidewall spacers with sizes and thicknesses different from each other. However, the conventional fabrication method cannot provide the sidewall spacers satisfying the requirements of each region. Since the sidewall spacers are formed in all regions under the conditions satisfying the requirements of only one region, the other regions cannot have a transistor which meets their requirements.